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[VHDL-FPGA-Verilog] Float

Description: 用VHDL语言在CPLD／FPGA上实现浮点运算，资源多多共享,不亦乐乎!-VHDL language used in the CPLD/FPGA to achieve floating-point operations, resources, a lot of sharing, joy!
Platform: | Size: 145408 | Author: wangzhe | Hits:

[Embeded-SCM Develop] VHDL_calendar

Description: 个人设计的基于VHDL的数字电子日历 在MAX+PLUSH软件平台上编译、仿真，最后将目标文件下载到CPLD中，经在实验装置上连线验证成功
Platform: | Size: 649216 | Author: 郭鑫俊 | Hits:

[VHDL-FPGA-Verilog] CPLD80386

Description: 使用CPLD仿真一个80383的CPU,很值得参考一下,难得-CPLD using a 80,383 emulation of CPU, is worth a reference, a rare
Platform: | Size: 236544 | Author: 梁志洪 | Hits:

[VHDL-FPGA-Verilog] eda

Description: 用VHDL编写的一个出租车计费器，起步6元计2公里，此后每半公里计0.8元，停车等待每2.5分计0.8元。通过仿真，但未下载到CPLD测试-Using VHDL prepared a taxi meter, starting 6 dollars two kilometers, and thereafter every half a kilometer of 0.8 yuan, parking to wait for every 2.5 hours of 0.8 yuan. Through simulation, but not downloaded to the CPLD test
Platform: | Size: 164864 | Author: 左大 | Hits:

[Embeded-SCM Develop] FPGA_CPLD

Description: 该PDF文档是CPLD/FPGA的入门教程。里面叙述了PLD的基本结构，选择CPLD/FPGA的方式方法。-The PDF document is the CPLD/FPGA introductory tutorial. Which describes the basic structure of PLD, select the CPLD/FPGA ways.
Platform: | Size: 192512 | Author: 李鑫旺 | Hits:

[VHDL-FPGA-Verilog] spi_master

Description: 基于CPLD/FPGA的SPI控制的IP核的实现spi_master-Based on CPLD/FPGA to control the SPI realize the IP core spi_master
Platform: | Size: 1024 | Author: linsky | Hits:

[VHDL-FPGA-Verilog] CPLD_raoma

Description: 基于CPLD的扰码与解扰码器的设计，扰码用M序列实现，m序列级数和频率可选-CPLD based on the scrambling code and Descrambling codec design, scrambling code sequence with M realize, m sequence of series and frequency optional
Platform: | Size: 39936 | Author: 梁奔山 | Hits:

[VHDL-FPGA-Verilog] an485_design_example

Description: AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）
Platform: | Size: 312320 | Author: zhiqiang | Hits:

[Embeded-SCM Develop] I2CCPLD

Description: I2C在CPLD上的模拟实现源程序,I2C在CPLD上的模拟实现源程序-I2C in CPLD realize the analog source, I2C in CPLD realize the analog source
Platform: | Size: 1024 | Author: zhp | Hits:

[VHDL-FPGA-Verilog] VHDLLCD1602

Description: 这个是VHDL语言编写的LCD1602程序@-This is the VHDL language LCD1602 procedure @
Platform: | Size: 546816 | Author: | Hits:

[Other] CPLD_ppt

Description: 对CPLD学习者有帮助，既讲解了硬件的结构，又讲述了VHDL语言的应用-CPLD learners to have help, both on the hardware structure, but also about the application of VHDL language
Platform: | Size: 812032 | Author: 秒年时微 | Hits:

[Embeded-SCM Develop] cpld

Description: 实现8通道模拟/数字转换和数字/模拟转换的例子,采用ISA总线控制逻辑.-Realize 8-channel analog/digital conversion and digital/analog converter example, the use of ISA bus control logic.
Platform: | Size: 3072 | Author: 兰升 | Hits:

[Software Engineering] VHDL

Description: 详细介绍了cpld技术的基础知识及其应用开发原理。-CPLD technology described in detail the basis of the principle of knowledge and its application development.
Platform: | Size: 4166656 | Author: 曹小中 | Hits:

[SCM] CPLD

Description: 控制三相步进电机及光电编码器的采集,当电机停止时,保证三相里面只有一相相通,防止停止时电流过大.-Control three-phase stepper motor and optical encoder collection, when the motor stops to ensure that only one phase of three-phase inside the heart, and to prevent too much current is stopped.
Platform: | Size: 580608 | Author: suifeg | Hits:

[SCM] CRC

Description: 循环冗余码校验（CRC）是一种可靠性很高的串行数据校验方法。介质循环冗余码校验的基本原理，并分别用单片机和CPLD作了循环冗余码验的软件实现和硬件实现。包括汇编语言和VHDL语言源程序-Cyclical redundancy check (CRC) is a high reliability of the serial data validation methods. Media cyclical redundancy check of the basic principles, and were made with MCU and CPLD Cyclic Redundancy Code inspection software and hardware realize realize. Including assembly language and VHDL language source
Platform: | Size: 14336 | Author: llhg | Hits:

[VHDL-FPGA-Verilog] DS18B20

Description: 用VHDL写的DS18B20温度采集程序，QuartusII的完整工程，控制灵活，易扩展-Using VHDL written DS18B20 temperature acquisition procedures, QuartusII complete projects, flexible control and easy expansion
Platform: | Size: 100352 | Author: wanyou | Hits:

[VHDL-FPGA-Verilog] FT245BM

Description: 这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序，用的是Verilog HDL语言-This is a MAX II CPLD module using USB transmit FT245BM reading and writing process, using Verilog HDL language
Platform: | Size: 975872 | Author: 杨林成 | Hits:

[VHDL-FPGA-Verilog] GetPcmSim

Description: PCM数据采集，CPLD部分。 写了很长时间了。 通过串口传送到PC。-PCM Data Acquisition, CPLD part. Wrote a very long time. Through the serial port to send to the PC.
Platform: | Size: 1041408 | Author: pancat | Hits:

[Other] sd_IP

Description: SD card controller can just read data using 1 bit SD mode. I have written this core for NIOS2 CPU, Cyclone, but I think it can works with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core. Good luck-SD card controller can just read data using 1 bit SD mode.I have written this core for NIOS2 CPU, Cyclone, but I think it can workswith other FPGA or CPLD. Better case for this core is SD clock = 20 MHz andCPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.Good luck
Platform: | Size: 8192 | Author: tuya | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: Verilog教程，讲述Verilog在cpld/fpga中从设计到仿真全过程。-Verilog tutorial, Verilog described in cpld/fpga simulation from the design to the entire process.
Platform: | Size: 2479104 | Author: pangyugang | Hits:
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